1. Field of the Invention
The present invention relates to a logic simulation apparatus for verifying the logic operation of a semiconductor integrated circuit in which a plurality of logic cells are connected.
2. Description of Related Art
A prior art logic simulation apparatus can shorten the time required for simulation by dividing the whole of target circuitry into some circuit portions according to the types of operation clocks, and by performing a simulation on each of the divided circuit portions with a necessary clock (see Japanese patent application publication (TOKKAIHEI) No. 9-73475 (column numbers [0025] to [0052] and FIG. 1)).
A problem encountered with a prior art logic simulation apparatus constructed as mentioned above is that because even if the target for simulation is a partial circuit that carries out a logic operation in synchronization with one clock domain, the prior art logic simulation apparatus verifies the logic of the partial circuit without neglecting occurring events, as in the case of a partial circuit that carries out a logic operation based on a plurality of clock domains, it takes much time to verify the logic of the partial circuit.